Project information
- Data Project: 2006-2009.
Category: Deep packet inspection security system for 10-Gbit network monitoring
device based on pattern matching algorithms implemented in FPGA devices.
Deep packet inspection security system for 10-Gbit network monitoring device based on pattern matching algorithms implemented in FPGA devices. FastMatch, FP6 project.
Highly integrated board equipped with two Virtex-5 devices (figure below). Board can be connected via AURORA interface to daughter board which consists two 10-Gig fiber tranceivers. FPGA chips are surrounded with different blocks of memeories (RLDRAM, DDR3) suitable for different tasks performed by board. Power supply chain of the board uses high performance Point-of-Load switching units from TI.